In existing PS/2 personal computer systems, the minimum pulse width for reliably detecting an I/O channel check or parity error is 100 ns. Micro Channel architecture now supports synchronous I/O channel check requiring the detection of pulses shorter than 100 ns. The detection circuit of the invention acquires pulses independently of the system clock, and allows a minimum pulse width for I/O channel check to be as low as approximately 10 ns, while simultaneously rejecting pulses below such minimum pulse width.
The invention is able to detect exceptions for both synchronous and asynchronous reporting of parity errors and I/O channel checks. Previous detector designs in earlier PS/2 computers did not permit detection of pulses of less than 100 ns duration on either input and were not capable of rejecting any glitches. Hence, exceptions by synchronous reporting could not be detected reliably. The previous designs relied on a 20 MHz clock to latch the inputs. With the invention, pulses of duration as low as 10 ns may now be specified, designed and detected reliably with no dependence on any clock. All pulses with larger than minimum width are now detected reliably. The minimum pulse width is determined by the internal logic of the chip and to a small extent by the physical layout. Glitch rejection is part of the new design. Since the Parity Error signal from main memory drives the Micro Channel I/O Channel Check signal, the invention also supports both methods of reporting exceptions. Therefore, the detection circuits for both inputs are designed in similar fashion.